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MC100LVE210, MC100E210 Low Voltage Dual 1:4, 1:5 Differential Fanout Buffer
ECL/PECL Compatible
The MC100LVE210 is a low voltage, low skew dual differential ECL fanout buffer designed with clock distribution in mind. The device features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device features fully differential clock paths to minimize both device and system skew. The dual buffer allows for the fanout of two signals through a single chip, thus reducing the skew between the two fundamental signals from a part-to-part skew down to an output-to-output skew. This capability reduces the skew by a factor of 4 as compared to using two LVE111's to accomplish the same task. The MC100LVE210 works from a -3.3V supply while the MC100E210 provides identical function and performance from a standard -4.5V 100E voltage supply. For applications which require a single-ended input, the VBB reference voltage is supplied. For single-ended input applications the VBB reference should be connected to the unused CLK input of a differential pair and bypassed to ground via a 0.01f capacitor. The input signal is then driven into the selected CLK input. To ensure that the tight skew specification is met it is necessary that both sides of the differential output are identically terminated, even if only one side is being used. In most applications all nine differential pairs will be used and therefore terminated. In the case where fewer than nine pairs are used it is necessary to terminate at least the output pairs adjacent to the output pair being used in order to maintain minimum skew. Failure to follow this guideline will result in small degradations of propagation delay (on the order of 10-20ps) of the outputs being used, while not catastrophic to most designs this will result in an increase in skew. Note that the package corners isolate outputs from one another such that the guideline expressed above holds only for outputs on the same side of the package. The MC100LVE210, as with most ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the LVE210 to be used for high performance clock distribution in +3.3V systems. Designers can take advantage of the LVE210's performance to distribute low skew clocks across the backplane or the board. In a PECL environment series or Thevenin line terminations are typically used as they require no additional power supplies, if parallel termination is desired a terminating voltage of VCC-2.0V will need to be provided. For more information on using PECL, designers should refer to Application Note AN1406/D. * Dual Differential Fanout Buffers * 200ps Part-to-Part Skew * 50ps Typical Output-to-Output Skew * Low Voltage ECL/PECL Compatible * 28-lead PLCC Packaging
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PLCC PACKAGE FN SUFFIX CASE 776
MARKING DIAGRAM*
MC100LVE210 AWLYYWW
A WL YY WW
= Assembly Location = Wafer Lot = Year = Work Week
MC100E210FN AWLYYWW
A WL YY WW
= Assembly Location = Wafer Lot = Year = Work Week
*For additional information, see Application Note AND8002/D
ORDERING INFORMATION
Device MC100LVE210FN MC100LVE210FNR2 MC100E210FN MC100E210FNR2 Package PLCC PLCC PLCC PLCC Shipping 37 Units / Rail 500 Tape & Reel 37 Units / Rail 500 Tape & Reel
(c) Semiconductor Components Industries, LLC, 1999
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February, 2000 - Rev. 2
Publication Order Number: MC100LVE210/D
MC100LVE210, MC100E210
Qa0 25 VEE VBB CLKa VCC CLKa CLKb CLKb 26 27 28 1 2 3 4 5 Qb4 6 7 8 9 10 11 Qb2 Qa0 Qa1 VCCO Qa1 Qa2 24 23 22 21 20 Qa2 19 18 17 16 Qa3 Qa3
PIN NAMES
Qb0 VCCO Qb0 Qb1 Qb1 Pins CLKa, CLKb Qa0:3, Qb0:4 VBB Function Differential Input Pairs Differential Outputs VBB Output
Pinout: 28-Lead PLCC (Top View)
15 14 13 12
Qb4 Qb3 VCCO Qb3 Qb2
LOGIC SYMBOL
Qa0 Qa0 CLKa CLKa Qa1 Qa1 Qa2 Qa2 Qa3 Qa3 Qb0 Qb0 CLKb CLKb Qb1 Qb1 Qb2 Qb2 Qb3 Qb3 Qb4 Qb4 VBB
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MC100LVE210, MC100E210
MC100LVE210 ECL DC CHARACTERISTICS
-40C Symbol VOH VOL VIH VIL VBB VEE IIH IEE Characteristic Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Output Reference Voltage Power Supply Voltage Input HIGH Current Power Supply Current Min -1.085 -1.830 -1.165 -1.810 -1.38 -3.0 Typ -1.005 -1.695 Max -0.880 -1.555 -0.880 -1.475 -1.26 -3.8 150 55 Min -1.025 -1.810 -1.165 -1.810 -1.38 -3.0 0C Typ -0.955 -1.705 Max -0.880 -1.620 -0.880 -1.475 -1.26 -3.8 150 55 Min -1.025 -1.810 -1.165 -1.810 -1.38 -3.0 25C Typ -0.955 -1.705 Max -0.880 -1.620 -0.880 -1.475 -1.26 -3.8 150 55 Min -1.025 -1.810 -1.165 -1.810 -1.38 -3.0 85C Typ -0.955 -1.705 Max -0.880 -1.620 -0.880 -1.475 -1.26 -3.8 150 65 Unit V V V V V V A mA
MC100LVE210 PECL DC CHARACTERISTICS
-40C Symbol VOH VOL VIH VIL VBB VCC IIH IEE Characteristic Output HIGH Voltage1 Output LOW Voltage1 Input HIGH Voltage1 Input LOW Voltage1 Output Reference Voltage1 Power Supply Voltage Input HIGH Current Power Supply Current Min 2.215 1.47 2.135 1.490 1.92 3.0 Typ 2.295 1.605 Max 2.42 1.745 2.420 1.825 2.04 3.8 150 55 Min 2.275 1.490 2.135 1.490 1.92 3.0 0C Typ 2.345 1.595 Max 2.420 1.680 2.420 1.825 2.04 3.8 150 55 Min 2.275 1.490 2.135 1.490 1.92 3.0 25C Typ 2.345 1.595 Max 2.420 1.680 2.420 1.825 2.04 3.8 150 55 Min 2.275 1.490 2.135 1.490 1.92 3.0 85C Typ 2.345 1.595 Max 2.420 1.680 2.420 1.825 2.04 3.8 150 65 Unit V V V V V V A mA
1. These values are for VCC = 3.3V. Level Specifications will vary 1:1 with VCC.
MC100LVE210 AC CHARACTERISTICS (VEE = VEE (min) to VEE (max); VCC = VCCO = GND)
-40C Symbol tPLH tPHL tskew Characteristic Propagation Delay to Output IN (differential) IN (single-ended) Within-Device SkewQa Qb Qa Qa,Qb Qb Part-to-Part Skew (Diff) Minimum Input Swing Common Mode Range Output Rise/Fall Time 500 -1.5 200 -0.4 600 Min 475 400 50 50 Typ Max 675 700 75 75 200 500 -1.5 200 -0.4 600 Min 475 400 50 30 0C Typ Max 675 700 75 50 200 500 -1.5 200 -0.4 600 Min 500 450 50 30 25C Typ Max 700 750 75 50 200 500 -1.5 200 -0.4 600 Min 500 450 50 30 85C Typ Max 700 750 75 50 200 ps Unit ps Note 1 Note 2 Note 3 Condition
VPP VCMR tr/tf
mV V ps
Note 4 Note 5 20%-80%
1. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential output signals. 2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. 3. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device. 4. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited for the LVE210 as a differential input as low as 50 mV will still produce full ECL levels at the output. 5. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to VPP(min).
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MC100LVE210, MC100E210
MC100E210 ECL DC CHARACTERISTICS
-40C Symbol VOH VOL VIH VIL VBB VEE IIH IEE Characteristic Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Output Reference Voltage Power Supply Voltage Input HIGH Current Power Supply Current Min -1.085 -1.830 -1.165 -1.810 -1.38 -5.25 Typ -1.005 -1.695 Max -0.880 -1.555 -0.880 -1.475 -1.26 -4.2 150 55 Min -1.025 -1.810 -1.165 -1.810 -1.38 -5.25 0C Typ -0.955 -1.705 Max -0.880 -1.620 -0.880 -1.475 -1.26 -4.2 150 55 Min -1.025 -1.810 -1.165 -1.810 -1.38 -5.25 25C Typ -0.955 -1.705 Max -0.880 -1.620 -0.880 -1.475 -1.26 -4.2 150 55 Min -1.025 -1.810 -1.165 -1.810 -1.38 -5.25 85C Typ -0.955 -1.705 Max -0.880 -1.620 -0.880 -1.475 -1.26 -4.2 150 65 Unit V V V V V V A mA
MC100E210 PECL DC CHARACTERISTICS
-40C Symbol VOH VOL VIH VIL VBB VCC IIH IEE Characteristic Output HIGH Voltage1 Output LOW Voltage1 Input HIGH Voltage1 Input LOW Voltage1 Output Reference Voltage1 Power Supply Voltage Input HIGH Current Power Supply Current Min 3.915 3.170 3.835 3.190 3.62 4.75 Typ 3.995 3.305 Max 4.12 3.445 4.12 3.525 3.74 5.25 150 55 Min 3.975 3.19 3.835 3.190 3.62 4.75 0C Typ 4.045 3.295 Max 4.12 3.38 4.12 3.525 3.74 5.25 150 55 Min 3.975 3.19 3.835 3.190 3.62 4.75 25C Typ 4.045 3.295 Max 4.12 3.38 4.12 3.525 3.74 5.25 150 55 Min 3.975 3.19 3.835 3.190 3.62 4.75 85C Typ 4.045 3.295 Max 4.12 3.38 4.12 3.525 3.74 5.25 150 65 Unit V V V V V V A mA
1. These values are for VCC = 5.0V. Level Specifications will vary 1:1 with VCC.
MC100E210 AC CHARACTERISTICS (VEE = VEE (min) to VEE (max); VCC = VCCO = GND)
-40C Symbol tPLH tPHL tskew Characteristic Propagation Delay to Output IN (differential) IN (single-ended) Within-Device SkewQa Qb Qa Qa,Qb Qb Part-to-Part Skew (Diff) Minimum Input Swing Common Mode Range Output Rise/Fall Time 500 -1.5 200 -0.4 600 Min 475 400 50 50 Typ Max 675 700 75 75 200 500 -1.5 200 -0.4 600 Min 475 400 50 30 0C Typ Max 675 700 75 50 200 500 -1.5 200 -0.4 600 Min 500 450 50 30 25C Typ Max 700 750 75 50 200 500 -1.5 200 -0.4 600 Min 500 450 50 30 85C Typ Max 700 750 75 50 200 ps Unit ps Note 1 Note 2 Note 3 Condition
VPP VCMR tr/tf
mV V ps
Note 4 Note 5 20%-80%
1. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential output signals. 2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. 3. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device. 4. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited for the E210 as a differential input as low as 50 mV will still produce full ECL levels at the output. 5. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to VPP(min).
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MC100LVE210, MC100E210
PACKAGE DIMENSIONS
PLCC PACKAGE FN SUFFIX CASE 776-02 ISSUE D
0.007 (0.180)
B -NY BRK U
M
T L -M
M
S
N
S S
0.007 (0.180)
T L -M
N
S
D Z -L-M-
W
V
D X VIEW D-D G1
0.010 (0.250)
S
T L -M
S
N
S
28
1
A
0.007 (0.180)
M
T L -M T L -M
S
N N
S
H
S
0.007 (0.180)
M
Z
T L -M
S
N
S
R
0.007 (0.180)
M
S
C
E
0.004 (0.100)
K1
G G1
0.010 (0.250)
J
-T-
SEATING PLANE
K F VIEW S
0.007 (0.180)
VIEW S
M
T L -M
S
N
S
S
T L -M
S
N
S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIM R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 -- 0.020 -- 0.025 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 0.020 -- 10 2 0.410 0.430 -- 0.040
MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.57 4.20 2.79 2.29 0.48 0.33 1.27 BSC 0.81 0.66 -- 0.51 -- 0.64 11.58 11.43 11.58 11.43 1.21 1.07 1.21 1.07 1.42 1.07 0.50 -- 10 2 10.42 10.92 -- 1.02
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MC100LVE210, MC100E210
Notes
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MC100LVE210, MC100E210
Notes
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MC100LVE210, MC100E210
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MC100LVE210/D

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